Lead ASIC SoC Design Engineer-
Architecture and Design Team, Front end Design and Architecture Silicon IP solutions.
SoC Front End Lead with 12+ years of experience
Micro-Architecture, RTL Design, Verification, RTL Quality checks, Synthesis, Constraints build, Timing closure.
Verilog, System Verilog RTL Coding,
Verification, debug using Xcelium and VCS simulators.
Managing hands-on multiple partitions and Top level.
Experience working with DFT, Physical Design teams in closing the design.
Constraint building, Timing Closure with Physical Design Team.
We ideally need looking for someone with extensive experience on designing and debugging Arm based SOCs.
• *** Ideally the candidate should possess Arm Neoverse CPU design, implementation knowledge; however we can consider Arm CPU based CPU subsystem design as Cortex A72/76 designs.
Specifically we should look for – micro-architecture, architecture, RTL design, debug, Arm NIC, CMN fabric.
"Hybrid work environment"
Location: San Jose, CA
Posted: Sept. 19, 2024, 11:51 p.m.
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